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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad8012 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999 dual 350 mhz low power amplifier functional block diagram 8 7 6 5 1 2 3 4 out1 Cin1 +in1 +v s out2 Cin2 +in2 Cv s ad8012 features low power 1.7 ma/amplifier supply current fully specified for 6 5 v and +5 v supplies high output current, 125 ma high speed 350 mhz, C3 db bandwidth (g = +1) 150 mhz, C3 db bandwidth (g = +2) 2,250 v/ m s slew rate 20 ns settling time to 0.1% low distortion C72 dbc worst harmonic @ 500 khz, r l = 100 v C66 dbc worst harmonic @ 5 mhz, r l = 1 k v good video specifications (r l = 1 k v , g = +2) 0.02% differential gain error 0.06 8 differential phase error gain flatness 0.1 db to 40 mhz 60 ns overdrive recovery low offset voltage, 1.5 mv low voltage noise, 2.5 nv/ ? hz available in 8-lead soic and 8-lead microsoic applications xdsl, hdsl line driver adc buffer professional cameras ccd imaging system ultrasound equipment digital camera product description the ad8012 is a dual low power current feedback amplifier capable of providing 350 mhz bandwidth while using only 1.7 ma per amplifier. it is intended for use in high frequency, wide dynamic range systems where low distortion, high speed are essential and low power is critical. with only 1.7 ma of supply current, the ad8012 also offers exceptional ac specs such as 20 ns settling time and 2,250 v/ m s slew rate. the video specifications are 0.02% differential gain and 0.06 degree differential phase, excellent for such a low power amplifier. in addition, the ad8012 has a low offset of 1.5 mv. the ad8012 is well suited for any application that requires high performance with minimal power. the product is available in standard 8-lead soic or m icro- soic packages and operates over the industrial temperature range C40 c to +85 c. r l C v C40 C90 10 1k 100 distortion C dbc C70 C80 C60 C50 g = +2 v out = 2v p-p r f = 750 v 3rd 2nd figure 1. distortion vs. load resistance, v s = 5 v, frequency = 500 khz amp 1 v in v ref r2 r1 r l = 100 v or 135 v v out np:ns transformer line power in db +v s + C Cv s + C figure 2. differential drive circuit for xdsl applications * * protected under u.s. patent number 5,537,079.
C2C rev. a ad8012Cspecifications dual supply parameter conditions min typ max units dynamic performance C3 db small signal bandwidth g = +1, v out < 0.4 v p-p, r l = 1 k w 270 350 mhz g = +2, v out < 0.4 v p-p, r l = 1 k w 95 150 mhz g = +2, v out < 0.4 v p-p, r l = 100 w 90 mhz 0.1 db bandwidth v out < 0.4 v p-p, r l = 1 k w /100 w 40/23 mhz large signal bandwidth v out = 4 v p-p 75 mhz slew rate v out = 4 v p-p 2,250 v/ m s rise and fall time v out = 2 v p-p 3 ns settling time 0.1%, v out = 2 v p-p 20 ns 0.02%, v out = 2 v p-p 35 ns overdrive recovery 2 overdrive 60 ns noise/harmonic performance distortion v out = 2 v p-p, g = +2 2nd harmonic 500 khz, r l = 1 k w /100 w C89/C73 dbc 5 mhz, r l = 1 k w /100 w C78/C62 dbc 3rd harmonic 500 khz, r l = 1 k w /100 w C84/C72 dbc 5 mhz, r l = 1 k w /100 w C66/C52 dbc output ip3 500 khz, d f = 10 khz, r l = 1 k w /100 w 30/40 dbm imd 500 khz, d f = 10 khz, r l = 1 k w /100 w C79/C77 dbc crosstalk 5 mhz, r l = 100 w C70 db input voltage noise f = 10 khz 2.5 nv/ ? hz input current noise f = 10 khz, +input, Cinput 15 pa/ ? hz differential gain f = 3.58 mhz, r l = 150 w /1 k w , g = +2 0.02/0.02 % differential phase f = 3.58 mhz, r l = 150 w /1 k w , g = +2 0.3/0.06 degrees dc performance input offset voltage 1.5 4mv t min Ct max 5mv open-loop transimpedance v out = 2 v, r l = 100 w 240 500 k w t min Ct max 200 k w input characteristics input resistance +input 450 k w input capacitance +input 2.3 pf input bias current +input, Cinput 3 12 m a +input, Cinput, t min Ct max 15 m a common-mode rejection ratio v cm = 2.5 v C56 C60 db input common-mode voltage range 3.8 4.1 v output characteristics output resistance g = +2 0.1 w output voltage swing 3.85 4v output current t min Ct max 70 125 ma short circuit current 500 ma power supply supply current/amp 1.7 1.8 ma t min Ct max 1.9 ma operating range dual supply 1.5 6.0 v power supply rejection ratio C58 C60 db specifications subject to change without notice. (@ t a = +25 8 c, v s = 6 5 v, g = +2, r l = 100 v , r f = r g = 750 v , unless otherwise noted)
C3C rev. a ad8012 (@ t a +25 8 c, v s = +5 v, g = +2, r l = 100 v , r f = r g = 750 v , unless otherwise noted) parameter conditions min typ max units dynamic performance C3 db small signal bandwidth g = +1, v out < 0.4 v p-p, r l = 1 k w 220 300 mhz g = +2, v out < 0.4 v p-p, r l = 1 k w 90 140 mhz g = +2, v out < 0.4 v p-p, r l = 100 w 85 mhz 0.1 db bandwidth v out < 0.4 v p-p, r l = 1 k w /100 w 43/24 mhz large signal bandwidth v out = 2 v p-p 60 mhz slew rate v out = 3 v p-p 1,200 v/ m s rise and fall time v out = 2 v p-p 2 ns settling time 0.1%, v out = 2 v p-p 25 ns 0.02%, v out = 2 v p-p 40 ns overdrive recovery 2 overdrive 60 ns noise/harmonic performance distortion v out = 2 v p-p, g = +2 2nd harmonic 500 khz, r l = 1 k w /100 w C87/C71 dbc 5 mhz, r l = 1 k w /100 w C77/C61 dbc 3rd harmonic 500 khz, r l = 1 k w /100 w C89/C72 dbc 5 mhz, r l = 1 k w /100 w C78/C52 dbc output ip3 500 khz, r l = 1 k w /100 w 30/40 dbm imd 500 khz, r l = 1 k w /100 w C77/C80 dbc crosstalk 5 mhz, r l = 100 w C70 db input voltage noise f = 10 khz 2.5 nv/ ? hz input current noise f = 10 khz, +input, Cinput 15 pa/ ? hz black level clamped to +2 v, f = 3.58 mhz differential gain r l = 150 w /1 k w 0.03/0.03 % differential phase r l = 150 w /1 k w 0.4/0.08 degrees dc performance input offset voltage 1 3mv t min Ct max 4mv open-loop transimpedance v out = 2 v p-p, r l = 100 w 200 400 k w t min Ct max 150 k w input characteristics input resistance +input 450 k w input capacitance +input 2.3 pf input bias current +input, Cinput 3 12 m a +input, Cinput, t min Ct max 15 m a common-mode rejection ratio v cm = 1.5 v to 3.5 v C56 C60 db input common-mode voltage range 1.5 to 3.5 1.2 to 3.8 v output characteristics output resistance g = +2 0.1 w output voltage swing 1 to 4 0.9 to 4.2 v output current t min Ct max 50 100 ma short circuit current 500 ma power supply supply current/amp 1.55 1.75 ma t min Ct max 1.85 ma operating range single supply 3 12 v power supply rejection ratio C58 C60 db specifications subject to change without notice. single supply
ad8012 C4C rev. a absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 v internal power dissipation 2 small outline package (r) . . . . . . . . . . . . . . . . . . . . . 0.8 w microsoic package (rm) . . . . . . . . . . . . . . . . . . . . . 0.6 w input voltage (common mode) . . . . . . . . . . . . . . . . . . . v s differential input voltage . . . . . . . . . . . . . . . . . . . . . . 2.5 v output short circuit duration . . . . . . . . . . . . . . . . . . . . . . observe power derating curves storage temperature range rm, r . . . . . . C65 c to +125 c operating temperature range (a grade) . . C40 c to +85 c lead temperature range (soldering 10 sec) . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for device in free air at +25 c 8-lead soic package: q ja = 155 c/w 8-lead microsoic package: q ja = 200 c/w maximum power dissipation the maximum power that can be safely dissipated by the ad8012 is limited by the associated rise in junction temperature. the m axi- mum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately +150 c. temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junction temperature of +175 c for an extended period can result in de- vice failure. the output stage of the ad8012 is designed for maximum load current capability. as a result, shorting the output to common can cause the ad8012 to source or sink 500 ma. to ensure proper operation, it is necessary to observe the maximum power derating curves. direct connection of the output to either power supply rail can destroy the device. ambient temperature C 8 c C50 0 t j = +150 8 c 2.0 1.5 1.0 maximum power dissipation C watts 8-lead soic package C40 C30 0 10203040506070 8090 8-lead microsoic 0.5 C20 C10 figure 3. plot of maximum power dissipation vs. temperature for ad8012 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8012 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device ordering guide temperature package package brand model range description options code ad8012ar C40 c to +85 c 8-lead soic so-8 ad8012ar-reel C40 c to +85 c13 tape and reel so-8 ad8012ar-reel7 C40 c to +85 c7 tape and reel so-8 ad8012arm C40 c to +85 c 8-lead microsoic rm-08 h6a AD8012ARM-REEL C40 c to +85 c13 tape and reel rm-08 h6a AD8012ARM-REEL7 C40 c to +85 c7 tape and reel rm-08 h6a
ad8012 C5C rev. a 0.1 m f 0.1 m f 10 m f 10 m f r l v in v out 750 v 750 v 49.9 v +v s Cv s + + figure 4. test circuit; gain = +2 20mv 5ns figure 5.* 100 mv step response; g = +2, v s = 2.5 v or 5 v, r l = 1 k w 1v 10ns figure 6. 4 v step response; g = +2, v s = 5 v, r l = 1 k w * note: v s = 2.5 v operat ion is identical to v s = +5 v single supply operation. 0.1 m f 0.1 m f 10 m f 10 m f r l v in v out 750 v 750 v 53.6 v +v s Cv s + + figure 7. test circuit; gain = C1 20mv 5ns figure 8.* 100 mv step response; g = C1, v s = 2.5 v or 5 v, r l = 1 k w 1v 10ns figure 9. 4 v step response; g = C1, v s = 5 v, r l = 1 k w typical performance characteristicsC
ad8012 C6C rev. a 20mv 5ns figure 10.* 100 mv step response; g = +2, v s = 2.5 v or 5 v, r l = 100 w 500mv 10ns figure 11. 2 v step response; g = +2, v s = 2.5 v, r l = 100 w 1v 10ns figure 12. 4 v step response; g = +2, v s = 5 v, r l = 100 w * note: v s = 2.5 v operat ion is identical to v s = +5 v single supply operation. 20mv 5ns figure 13.* 100 mv step response; g = C1, v s = 2.5 v or 5 v, r l = 100 w 500mv 10ns figure 14. 2 v step response; g = C1, v s = 2.5 v, r l = 100 w 1v 10ns figure 15. 4 v step response; g = C1, v s = 5 v, r l = 100 w
ad8012 C7C rev. a r l C v C40 C90 10 1k 100 distortion C dbc C70 C80 C60 C50 g = +2 v out = 2v p-p r f = 750 v 3rd 2nd figure 16. distortion vs. load resistance; v s = 5 v, frequency = 500 khz 3rd r l = 1k v frequency 2 mhz distortion 2 dbc 1 10 20 2nd r l = 1k v 3rd r l = 100 v 2nd r l = 100 v C40 C60 C80 C100 g = +2 v out = 2v p-p r f = 750 v figure 17. distortion vs. frequency; v s = 5 v frequency 2 mhz 0.1 10 100 g = +2 v o = 0.3v p-p r f = 750 v r l = 100 v v s = 6 5v 1 0.3 C0.3 0.2 C0.1 0.1 0 C0.2 C0.4 C0.5 0.4 0.5 normalized gain 2 db figure 18. gain flatness; v s = 5 v r l C v C40 C90 10 1k 100 distortion C dbc C70 C80 C60 C50 g = +2 v out = 2v p-p r f = 750 v 2nd 3rd figure 19. distortion vs. load resistance; v s = +5 v, frequency = 500 khz C40 C100 10 20 distortion C dbc C80 C60 g = +2 v out = 2v p-p r f = 750 v frequency C mhz 1 3rd r l = 1k v 2nd r l = 1k v 3rd r l = 100 v 2nd r l = 100 v figure 20. distortion vs. frequency; v s = +5 v frequency 2 mhz 0.1 10 100 g = +2 v o = 0.3v p-p r f = 750 v r l = 100 v v s = +5v 1 0.3 C0.3 0.2 C0.1 0.1 0 C0.2 C0.4 C0.5 0.4 0.5 normalized gain 2 db figure 21. gain flatness; v s = +5 v
ad8012 C8C rev. a frequency 2 mhz 3 C3 100 500 2 C1 v o = 0.3v p-p r f = 750 v r l = 100 v v s = 6 5v 1 0 C2 C4 4 5 g = +10 g = +2 g = +1 C5 10 1 normalized gain 2 db figure 22. frequency response; v s = 5 v frequency 2 mhz 3 C15 100 500 0 C9 g = +2 r f = 750 v r l = 100 v v s = 6 5v C3 C6 C12 C18 6 9 C21 10 1 output voltage 2 dbv 1v rms figure 23. output voltage vs. frequency; v s = 5 v, g = +2 v, r l = 100 w frequency C mhz C20 C80 100 500 C30 C60 v in = 0.2v p-p v s = 6 5v, +5v C40 C50 C70 C90 C10 0 1 0.03 0.1 10 cmrr 2 db C100 figure 24. cmrr vs. frequency; v s = 5 v, +5 v frequency C mhz normalized gain 2 db 3 C3 100 500 2 C1 v o = 0.3v p-p r f = 750 v r l = 100 v v s = +5v 1 0 C2 C4 4 5 g = +10 g = +2 g = +1 C5 10 1 figure 25. frequency response; v s = +5 v frequency 2 mhz output voltage 2 dbv C3 C21 100 500 C6 C15 g = +2 r f = 750 v r l = 100 v v s = +5v C9 C12 C18 C24 0 3 C27 10 1 1vrms figure 26. output voltage vs. frequency; v s = +5 v, g = +2 v, r l = 100 w 0 C10 C20 C30 C40 C60 C70 C80 100k 1m 10m 100m 500m frequency C hz C50 C90 C100 psrr C db v s = +5v or 6 5v g = +2 r f = 750 v Cpsrr +psrr figure 27. psrr vs. frequency; v s = 5 v, +5 v
ad8012 C9C rev. a frequency C mhz output resistance 2 v 100 0.1 100 500 1 10 1k 0.01 1 0.03 0.1 10 v s = 6 5v v s = +5v g = +2 r f = 750 v figure 28. output resistance vs. frequency 1e+03 1e+04 1e+05 1e+06 1e+07 1e+08 1e+09 135 115 95 75 55 15 C5 frequency 2 hz 35 t z 2 db v 0 phase C degrees C40 C80 C120 C160 C200 C240 C280 t z (s) phase figure 29. ope n-loop transi mpedance and phase vs. frequency load C v 10 1k 10k 100 7 1 6 3 5 4 2 0 8 9 swing C v p-p +5v 6 5v figure 30. output swing vs. load frequency C hz 100 10k 1k 3.6 2.4 3.4 2.8 3.2 3.0 2.6 2.2 2.0 3.8 4.0 current noise +in/Cin voltage noise 26 14 24 18 22 20 16 12 10 28 30 input current noise C pa/ hz 100k input voltage noise C nv/ hz figure 31. noise vs. frequency 9 8 7 6 5 4 3 2 3 4 5 6 7 8 9 10 11 1 0 f = 5mhz g = 1 2 r f = 750 v r l = 100 v r l = 1k v total supply voltage 2 volts peak-to-peak output at 5mhz ( # 1% thd) 2 v figure 32. output swing vs. supply 0.1% 5ns g = +2 r f = 750 v r l = 100 v 2v step t = 0 output voltage error C 0.1%/div figure 33. settling time, v s = 5 v
ad8012 C10C rev. a frequency C mhz 3 C3 100 500 2 C1 v o = 0.3v p-p r f = 750 v r l = 1k v 1 0 C2 C4 4 5 g = +10 g = +2 g = +1 C5 10 1 normalized gain 2 db figure 34. frequency response; v s = 5 v 0.3 C0.3 0.2 C0.1 v o = 0.3v p-p g = +2 r f = 750 v r l = 1k v 0.1 0 C0.2 C0.4 0.4 0.5 C0.5 frequency C mhz 0.1 10 1 100 normalized gain C db figure 35. gain flatness; v s = 5 v frequency C mhz input referred error C db C40 C100 100 500 C50 C80 C60 C70 C90 C110 C30 C20 C120 1 0.03 0.1 10 side 1 side 2 driver v o = 2v p-p r l = 100 v figure 36. crosstalk vs. frequency frequency C mhz 3 C3 100 500 2 C1 v o = 0.3v p-p r f = 750 v r l = 1k v 1 0 C2 C4 4 5 g = +10 g = +2 g = +1 C5 10 1 normalized gain 2 db figure 37. frequency response; v s = +5 v normalized gain C db 0.3 C0.3 0.2 C0.1 v o = 0.3v p-p r f = 750 v r l = 1k v 0.1 0 C0.2 C0.4 0.4 0.5 C0.5 frequency C mhz 0.1 10 1 100 figure 38. gain flatness; v s = +5 v v out , 2v/div 20ns +3v 0v 0v v out v out v in v in 0v 0v C3v figure 39. overdrive recovery; v s = 5 v, g = +2, r f = 750 w , r l = 100 w , v in = 3 v p-p (t = 1 m s)
ad8012 C11C rev. a theory of operation the ad8012 is a dual high speed cf amplifier that attains new levels of bandwidth (bw), power, distortion and signal swing capability. its wide dynamic performance (including noise) is the result of both a new complementary high speed bipolar process and a new and unique architectural design. the ad8012 basically uses a two gain stage complementary design approach versus the traditional single stage complementary mirror structure sometimes referred to as the nelson amplifier. though twin stages have been tried before, they typically consumed high power since they were of a folded cascade design much like the ad9617. this design allows for the standing or quiescent current to add to the high signal or slew current-induced stages. in the time domain, the large signal output rise/fall time and slew rate is typically controlled by the small signal bw of the amplifier and the input signal step amplitude respectively, not the dc quiescent current of the gain stages (with the exception of input level shift diodes q1/q2). using two stages vs. one also allows for a higher overall gain bandwidth product (gbwp) for the same power, thus lower signal distortion and the ability to drive heavier external loads. in addition, the second gain stage also isolates (divides down) a3s input reflected load drive and the nonlinearities created resulting in relatively lower dis- tortion and higher open-loop gain. overall, when high external load drive and low ac distortion is a requirement, a twin gain stage integrating amplifier like the ad8012 will provide excellent results for lower power over the traditional single stage complementary devices. in addition, being a cf amplifier, closed-loop bw variations versus exter- nal gain variations (varying rn) will be much lower compared to a vf op amp, where the bw varies inversely with gain. an- other key attribute of this amplifier is its ability to run on a single 5 v supply due in part to its wide common-mode input and output voltage range capability. for 5 v supply operation, the device obviously consumes half the quiescent power (vs. 10 v supply) with little degradation in its ac and dc perfor- mance characteristics. see data sheet comparisons. dc gain characteristics gain stages a1/a1b and a2/a2b combined provide negative feedforward transresistance gain. see figure 40. stage a3 is a unity gain buffer which provides external load isolation to a2. each stage uses a symmetrical complementary design. (a3 is also complementary though not explicitly shown). this is done to reduce both second order signal distortion and overall quies- cent power as discussed above. in the quasi dc to low frequency region, the closed loop gain relationship can be approximated as: g = 1+ r f / r n noninverting operation g = C r f / r n inverting operation these basic relationships above are common to all traditional operational amplifiers. v p q1 q2 ipp ipn inp ipn v n a1 a1 z i iq1 q3 q4 ie c p 1 c p 1 z2 a2 c l r n icq C io r f v o c d icq + io v o 9 iq1 ad8012 a2 c p 2 z1 = r1 || c1 z1 c d a3 r l z1 Cv i Cv i ir C ifc ir + ifc +C figure 40. simplified block diagram
ad8012 C12C rev. a applications line driving for hdsl high bitrate digital subscriber line (hdsl) is becoming popular as a means of providing full duplex data communication at rates up to 1.544 mbps or 2.048 mbps over moderate dis- tances via conventional telephone twisted pair wires. traditional t1 (e1 in europe) requires repeaters every 3,000 feet to 6,000 feet to boost the signal strength and allow transmission over distances of up to 12,000 feet. in order to achieve repeaterless transmission over this distance, an hdsl modem requires transmitted power level of +13.5 dbm (assuming a line imped- ance of 135 w ). hdsl uses the two binary/one quaternary line code (2b1q). a sample 2b1q waveform is shown in figure 41. the digital bit stream is broken up into groups of two bits. four analogue voltages (called quaternary symbols) are used to represent the four possible combinations of two bits. these symbols are as- signed arbitrary names +3, +1, C1 and C3. the corresponding voltage levels are produced by a dac that is usually part of an analog front end circuit (afec). before being applied to the line, the dac output is low-pass filtered and acquires the sinu- soidal form shown in figure 41. finally, the filtered signal is applied to the line driver. the line voltages that correspond to the quaternary symbols +3, +1, C1 and C3 are 2.64 v, 0.88 v, C0.88 v and C2.64 v. this gives a peak-to-peak line voltage of 5.28 v. voltage +3 2.64v +1 0.88v C1 C0.88v C3 C2.64v symbol name dac output filtered output to line driver C1 01 +3 10 +1 11 C3 00 C3 00 +1 11 +3 10 C3 00 C1 01 C1 01 +1 11 C1 01 C3 00 figure 41. time domain representation of a hdsl signal many of the elements of a classic differential line driver are shown in the hdsl line driver in figure 42. a 6 v peak-to- peak differential signal is applied to the input. the differential gain of the amplifier (1+2 r f /r g ) is set to +2, so the resulting differential output signal is 12 v p-p. as is normal in telephony applications, a transformer galvani- cally isolates the differential amplifier from the line. in this case a 1:1 turns ratio is used. in order to correctly terminate the line, it is necessary to set the output impedance of the amplifier to be equal to the impedance of the line being driven (135 w in this case). because the transformer has a turns ratio of 1:1, the im- pedance reflected from the line is equal to the line impedance of 135 w (r refl = r line /turns ratio 2 ). as a result, two 66.5 w resistors correctly terminate the line. 6v p-p 12v p-p 1:1 +5v C5v r f 750 v r f 750 v r g 1.5k v 1/2 ad8012 1/2 ad8012 0.1 m f 0.1 m f 66.5 v 66.5 v 6v p-p 1:1 135 v to receiver circuitry to receiver circuitry gain = +2 up to 12,000 feet + C figure 42. differential for hdsl applications the immediate effect of back-termination is that the signal from the amplifier is halved before being applied to the line. this doubles the power the amplifier must deliver. however, the back-termination resistors also play an important second role. full-duplex data transmission systems like hdsl simulta- neously transmit data in both directions. as a result, the signal on the line and across the back termination resistors is the com- posite of the transmitted and received signal. the termination resistors are used to tap off this signal and feed it to the receive circuitry. because the receive circuitry knows what is being transmitted, the transmitted data can be subtracted from the digitized composite signal to reveal the received data. driving a line with a differential signal offers a number of ad- vantages compared to a single-ended drive. because the two outputs are always 180 degrees out of phase relative to one another, the differential signal output is double the output am- plitude of either of the op amps. as a result, the differential amplifier can have a peak-to-peak swing of 16 v (each op amp can swing to 4 v), even though the power supply is 5 v. in addition to this, even-order harmonics (2nd, 4th, 6th, etc.) of the two single-ended outputs tend to cancel out one another, so the total harmonic distortion (quadratic sum of all har monics) decreases compared to the single-ended case, even as the signal amplitude is doubled. this is particularly advantageous for the case of the second harmonic. as it is very close to the funda- mental, filtering becomes difficult. in this application, the thd is dominated by the third harmonic which is 65 db below the carrier (i.e., spurious free dynamic range = C65 dbc). differential line driving also helps to preserve the integrity of the transmitted signal in the presence of electro-magnetic in- terference (emi). emi tends to induce itself equally on to both the positive and negative signal line. as a result, a receiver with good common-mode rejection, will amplify the original signal while rejecting induced (common-mode) emi.
ad8012 C13C rev. a choosing the appropriate turns ratio for the transformer increasing the peak-to-peak output signal from the amplifier in the previous example, combined with a variation in the turns ratio of the transformer, can yield further enhancements to the circuit. the output signal swing of the ad8012 can be increased to about 3.9 v before clipping occurs. this increases the peak- to-peak output of the differential amplifier to 15.6 v. because the signal applied to the primary winding is now bigger, the transformer turns ratio of 1:1 can be replaced with a (step- down) turns r atio of about 1.3:1 (from amplifier to line). this steps the 7.8 v peak-to-peak primary voltage down to 6 v. this is the same secondary voltage as before so the resulting power delivered to the line is the same. the received signal, which is small relative to the transmi tted signal, will, however be stepped up by a factor of 1.3. amplifying the received signal in this manner enhances its signal-to-noise ratio and is useful when the received signal is small compared to the to-be-transmitted signal. the impedance reflected from the 135 w line now becomes 228 w (1.3 2 times 135 w ). with a correctly terminated line, the amplifier must now drive a total load of 456 w (114 w + 114 w + 228 w ), considerably less than the original 270 w load. this reduces the drive current from the op amps by about 40%. more significant however is the reduction in dynamic power consumption; that is, the power the amplifier must consume in order to deliver the load power. increasing the output signal so that it is as close as possible to the power rails, minimizes the power consumed in the amplifier. there is, however, a price to pay in terms of increased signal distortion. increasing the output signal of each op amp from the original 3 v to 3.9 v reduces the spurious free dynamic range (sfdr) from C65 db to C50 db (measured at 500 khz), even though the overall load impedance has increased from 270 w to 456 w . layout considerations the specified high speed performance of the ad8012 requires careful attention to board layout and component selection. table i shows recommended component values for the ad 8012 and figures 44C49 show recommended layouts for the 8-lead soic and microsoic packages for a positive gain. proper rf design techniques and low parasitic component s elections are mandatory. table i. typical bandwidth vs. gain setting resistors small signal C3 db bw (mhz), gain r f r g r t v s = 6 5 v, r l = 1 k v C1 750 w 750 w 53.6 w 110 +1 750 w C 49.9 w 350 +2 750 w 750 w 49.9 w 150 +10 750 w 82.5 w 49.9 w 40 r t chosen for 50 w characteristic input impedance. the pcb should have a ground plane covering all unused por- tions of the component side of the board to provide a low im- pedance ground path. the ground plane should be removed from the area near the input pins to reduce stray capacitance. chip capacitors should be used for supply bypassing (see fig- ure 43). one end should be connected to the ground plane and the other within 1/8 in. of each power pin. an additional (4.7 m fC10 m f) tantalum electrolytic capacitor should be con- nected in parallel. the feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a minimum. capacitance greater than 1.5 pf at the inverting input will significantly affect high speed performance when operating at low noninverting gains. stripline design techniques should be used for long signal traces (greater than about 1 in.). these should be designed with the proper system characteristic impedance and be properly termi- nated at each end. 0.1 m f inverting configuration v out r f r o * 10 m f noninverting configuration v out r g r f r o * r t 0.1 m f 10 m f r t v in r g v in *r o chosen for characteristic impedance. *r o chosen for characteristic impedance. +v s + + Cv s figure 43. inverting and noninverting configurations
ad8012 C14C rev. a figure 44. universal soic noninverter top silkscreen figure 45. universal soic noninverter top figure 46. universal soic noninverter bottom figure 47. universal microsoic noninverter top silkscreen figure 48. universal microsoic noninverter top figure 49. universal microsoic noninverter bottom
ad8012 C15C rev. a 8-lead soic (so-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 4 1 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 8-lead microsoic (rm-08) 8 5 4 1 0.122 (3.10) 0.114 (2.90) 0.199 (5.05) 0.187 (4.75) pin 1 0.0256 (0.65) bsc 0.122 (3.10) 0.114 (2.90) seating plane 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) 0.008 (0.20) 0.043 (1.09) 0.037 (0.94) 0.120 (3.05) 0.112 (2.84) 0.011 (0.28) 0.003 (0.08) 0.028 (0.71) 0.016 (0.41) 33 27 0.120 (3.05) 0.112 (2.84) outline dimensions dimensions shown in inches and (mm). c3207aC0C12/99 printed in u.s.a.

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